This invention relates to data transfer through a bridge device.
A peripheral component interconnect (PCI) bus is a local bus inside a computer system. A PCI-to-PCI (P2P) bridge is a device that connects two independent PCI buses.
There can be a latency in establishing connections through a P2P bridge. One possible source of acquisition latency may be associated with making a connection to a dynamic random access memory (DRAM). Another source of acquisition latency is associated with the time required to acquire the buses for transactions. The DRAM acquisition latency causes buses to be held in a wait state even though they may be in alignment and ready to receive the DRAM data. These wait states reduce the effective bandwidth of the bridge and lengthen the bus acquisition latency for other agents wishing to conduct transactions on those buses, reducing the overall performance of a computer""s IO subsystem.